The disclosed subject matter relates generally to manufacturing and testing of semiconductor devices, more particularly, to identifying manufacturing disturbances using preliminary electrical test data.
There is a constant drive within the semiconductor industry to increase the quality, reliability and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in a continual improvement in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost of integrated circuit devices incorporating such transistors.
Generally, a distinct sequence of processing steps is performed on a lot of wafers using a variety of processing tools, including photolithography steppers, etch tools, deposition tools, polishing tools, rapid thermal processing tools, implantation tools, etc., to produce final products that meet certain electrical performance requirements. In some cases, electrical measurements that determine the performance of the fabricated devices are not conducted until relatively late in the fabrication process, and sometimes not until the final test stage. For example, it is not uncommon for six weeks to lapse between the completion of quality significant steps and the final wafer electrical testing (FWET).
Prior to completion of the device (e.g., prior to forming the final metalization layers), a sample wafer electrical test (SWET) may be performed. SWET testing may be performed after completion of manufacturing steps that significantly impact quality of the yet to be completed devices. SWET measurements typically encompass dozens or even hundreds of parameters. It is difficult to monitor this large number of signals, and it is common to fail to identify error signals in the data. This difficulty is compounded by the fact that it is difficult to correlate the SWET disturbances to actual quality parameters in the completed device. As a result, significant signals identifying a problem may be missed, which may lead to a reduction on product quality, and resources may be expended unproductively by investigating false alarms, which increases cost and may reduce throughput.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.